View HM6287HM6287HSERIES_179165.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HM6287, HM6287H Series
65536-word x 1-bit High Speed CMOS Static RAM
Description
The Hitachi HM6287/HM6287H is a high speed 64 k static RAM organized as 64-kword x 1-bit. It realizes high speed access time (25/35/45/55/70 ns) and low power consumption, employing CMOS process technology and high speed circuit design technology. It is most advantageous for high speed and high density memory, such as cache memory for mainframes or 32-bit MPUs. The HM6287/HM6287H is packaged in a 300-mil plastic DIP and SOJ, and is available for high density mounting. The low power version retains data with battery backup.
Features
* Single 5 V supply and high density 22-pin DIP and 24-pin SOJ * High speed: Fast access time 25/35/45/55/70 ns (max) * Low power Operation: 300 mW (typ) Standby: 100 W (typ)/10 W (typ) (L-version) * Completely static memory * No clock or timing strobe required * Equal access and cycle times * Directly TTL compatible: All inputs and outputs * Battery backup capability (L-version)
HM6287, HM6287H Series
Ordering Information
Type No. HM6287P-45 HM6287P-55 HM6287P-70 HM6287LP-45 HM6287LP-55 HM6287LP-70 HM6287HP-25 HM6287HP-35 HM6287HLP-25 HM6287HLP-35 HM6287HJP-25 HM6287HJP-35 HM6287HLJP-25 HM6287HLJP-35 Access Time 45 ns 55 ns 70 ns 45 ns 55 ns 70 ns 25 ns 35 ns 25 ns 35 ns 25 ns 35 ns 25 ns 35 ns 300-mil, 24-pin SOJ (CP-24D) 300-mil, 22-pin plastic DIP (DP-22NB) Package 300-mil, 22-pin plastic DIP (DP-22N)
Pin Arrangement
HM6287P/HP Series A0 A1 A2 A3 A4 A5 NC A6 A7 Dout WE VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 (Top view) VCC A15 A14 A13 A12 NC A11 A10 A9 A8 Din CS A0 A1 A2 A3 A4 A5 A6 A7 Dout WE VSS 1 2 3 4 5 6 7 8 9 10 11 (Top view) 22 21 20 19 18 17 16 15 14 13 12 VCC A15 A14 A13 A12 A11 A10 A9 A8 Din CS HM6287HJP
2
HM6287, HM6287H Series
Pin Description
Pin Name A0-A15 Din Dout CS WE VCC VSS Function Address Input Output Chip select Write enable Power supply Ground
Block Diagram
A0 A1 A2 A3 A4 A5 A6 Din CS WE
VCC Row decoder Memory array 128 x 512 VSS
Column I/O Column decoder
Dout
A7
A15
Truth Table
CS H L L WE x H L Mode Standby Read Write VCC current I SB , I SB1 I CC I CC Dout pin High-Z Dout High-Z Ref. Cycle -- Read cycle 1, 2 Write cycle 1, 2
Note: x: Don't care.
3
HM6287, HM6287H Series
Absolute Maximum Ratings
Parameter Voltage any pin relative to VSS Power dissipation Operating temperature Storage temperature Storage temperature under bias Symbol VT PT Topr Tstg Tbias Value -0.5 to +7.0 1.0 0 to +70 -55 to +125 -10 to +85
*
Unit V W C C C
Note: VT min: -3.5 V for pulse width 20 ns (HM6287 Series) VT min: -2.0 V for pulse width 10 ns (HM6287H Series)
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Symbol VCC VSS Input high (logic 1) voltage Input low (logic 0) voltage Note: VIH VIL Min 4.5 0 2.2 -0.5
*1
Typ 5.0 0 -- --
Max 5.5 0 6.0 0.8
Unit V V V V
1. VIL min: -3.0 V for pulse width 20 ns (HM6287 Series) VIL min: -2.0 V for pulse width 10 ns (HM6287H Series)
DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)
HM6287 Parameter Input leakage current Output leakage current Operating VCC current Standby V CC current Symbol Min |ILI| |ILO | I CC I SB -- -- -- -- -- -- -- 2.4 Typ* -- -- 60 10
1
HM6287H Max 2.0 2.0 100 30 Min -- -- -- -- -- -- -- 2.4 Typ*1 -- -- 60 15 Max 2.0 2.0 120 30 Unit Test Conditions A A mA mA mA mA V V VCC = Max Vin = VSS to V CC CS = VIH, VI/O = VSS to V CC CS = VIL, Iout = 0 mA, min cycle CS = VIH, min. cycle CS V CC - 0.2 V 0 V Vin 0.2 V or V CC - 0.2 V V in I OL = 8 mA I OH = -4.0 mA
Standby V CC current (1) I SB1
0.02 2.0 0.02 *2 0.1 *2 -- -- 0.4 --
0.02 2.0 0.02 *2 0.1 *2 -- -- 0.4 --
Output low voltage Output high voltage
VOL VOH
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25C and not guaranteed. 2. These characteristics are guaranteed only for L-version.
4
HM6287, HM6287H Series
Capacitance (Ta = 25C, f = 1.0 MHz)*1
HM6287 Parameter Input capacitance Output capacitance Note: Symbol Cin Cout Min -- -- Max 5 7.5 HM6287H Min -- -- Max 6 8 Unit pF pF Test Conditions Vin = 0 V Vout = 0 V
1. These parameters are sampled and not 100% tested.
AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, unless otherwise noted.)
Test Conditions * * * * Input pulse levels: VSS to 3.0 V Input and output timing reference levels: 1.5 V Input rise and fall time: 5 ns Output load: See figure
+5V 480 Dout 255 Dout 255 +5V 480
30 pF *1
5 pF *1
Output load (A)
Output load (B) (for tHZ, tLZ, tWZ and tOW )
Note: 1. Including scope and jig
5
HM6287, HM6287H Series
Read Cycle
HM6287H- HM6287H- HM628725 35 45 Parameter Read cycle time Address access time Chip select access time Symbol Min t RC t AA t ACS 25 -- -- 3 5 0 0 -- HM628755 HM628770
Max Min Max Min Max Min Max Min Max Unit Notes -- 25 25 -- -- 12 -- 25 35 -- -- 5 5 0 0 -- -- 35 35 -- -- 20 -- 30 45 -- -- 5 5 0 0 -- -- 45 45 -- -- 30 -- 40 55 -- -- 5 5 0 0 -- -- 55 55 -- -- 30 -- 40 70 -- -- 5 5 0 0 -- -- 70 70 -- -- 30 -- 40 ns ns ns ns ns ns ns ns 1, 3, 4 1, 3, 4 4 4 2
Output hold from address t OH change Chip selection to output in t LZ low-Z Chip deselection to output t HZ in high-Z Chip selection to powerup time t PU
Chip deselection to power t PD down time
Notes: 1. Transistion is measured +200 mV from steady state voltage with load (B). 2. All read cycle timing is referenced from last valid address to the first transitioning address. 3. At any given temperature and voltage condition, t HZ max, is less the t LZ min both for a given device and from device to device. 4. These parameters are sampled and not 100% tested.
Read Timing Waveform (1)
tRC
Address tAA tOH Dout Previous data valid Valid Data tOH
Notes: 1. WE is high for read cycle. 2. Device is continously selected, CS = VIL. 3. All read cycle timing is referred from last valid address to the first transitioning address.
6
HM6287, HM6287H Series
Read Timing Waveform (2)
tRC CS tACS tLZ Dout VCC supply current High impedance tPU ICC ISB Notes: 1. WE is high for read cycle. 2. Address valid prior to or coincident with CS transistion low. 50% Valid Data tPD 50% High impedance tHZ
Write Cycle
HM6287H- HM6287H- HM628725 35 45 Parameter Write cycle time Chip selection to endof write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time Symbol t WC t CW t AW t AS t WP t WR t DW t DH HM628755 HM628770
Min Max Min Max Min Max Min Max Min Max Unit Notes 25 20 20 0 20 0 15 0 0 5 -- -- -- -- -- -- -- -- 8 -- 35 30 30 0 30 0 20 0 0 5 -- -- -- -- -- -- -- -- 10 -- 45 40 40 0 25 0 25 0 0 0 -- -- -- -- -- -- -- -- 25 -- 55 50 50 0 35 0 25 0 0 0 -- -- -- -- -- -- -- -- 25 -- 70 55 55 0 40 0 30 0 0 0 -- -- -- -- -- -- -- -- 30 -- ns ns ns ns ns ns ns ns ns ns 2 2 1
Write enabled to output in t WZ high-Z Output active from end of t OW write
Notes: 1. All write cycle timing is referenced from the last valid address to first transitioning address. 2. Transition is measured 200 mV from steady state voltage with load B. These parameters are sampled and not 100% tested.
7
HM6287, HM6287H Series
Write Timing Waveform (1) (WE Controlled)
tWC Address tCW CS tAW tAS WE tDW Din tWZ Dout Valid Data tOW High impedance tOH *3 tDH tWP *1 tWR *2
Notes: 1. A write occurs during the overlap of a low CS and a low WE (tWP). 2. tWR is measured from the earlier of CS or WE going high to the end of the write cycle. 3. Dout is the same phase of write data of this write cycle, if tWR is long enough.
8
HM6287, HM6287H Series
Write Timing Waveform (2) (CS Controlled)
tWC Address tAW tAS tCW CS tWP *1 WE tDW Din Valid Data High impedance *3 Dout Notes: 1. A write occurs during the overlap of a low CS and a low WE (tWP). 2. tWR is measured from the earlier of CS or WE going high to the end of the write cycle. 3. If CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output buffers remain in a high impedance state. tDH tWR *2
9
HM6287, HM6287H Series
Low VCC Data Retention Characteristics (Ta = 0 to +70C)
These specifications are guaranteed only for L-version.
Parameter VCC for data retention Symbol VDR Min 2.0 Typ -- Max -- Unit V Test conditions CS V CC - 0.2 V, 0 V Vin - 0.2 V, or 0 V Vin 0.2V
Data retention current
I CCDR
-- --
-- -- --
*1
50*2 35 -- --
*3
A A ns ns See retention waveform
Chip deselect to data retention time Operation recovery time Notes: 1. t RC = Read cycle time 2. VCC = 3.0 V 3. VCC = 2.0 V
t CDR tR
0 t RC
--
Low V CC Data Retention Waveform
Data retention mode 4.5 V tCDR 2.2 V CS 0V VDR CS VDR - 0.2 V tR
VCC
10
HM6287, HM6287H Series
Package Dimensions
HM6287P/LP Series (DP-22N)
27.08 27.90 Max 22 12 6.60 7.00 Max
Unit: mm
1 0.88 1.30 Max 1.3
11
0.51 Min
2.54 Min
5.08 Max
7.62
2.54 0.25
0.48 0.10
0.25 - 0.05 0 - 15
+ 0.11
HM6287HP/HLP Series (DP-22NB)
27.08 27.90 Max 22 12 6.60 7.00 Max
Unit: mm
1 0.88 1.30 Max 1.3
11
2.54 Min 5.08 Max
7.62
0.51 Min
2.54 0.25
0.48 0.10
0.25 - 0.05 0 - 15
+ 0.11
11
HM6287, HM6287H Series
HM6287HJP/HLJP Series (CP-24D)
15.63 16.00 Max 24 13 7.62 0.13 8.64 0.13
Unit: mm
1
0.74
12 3.50 0.26
0.21 2.40 + 0.24 -
1.30 Max
0.43 0.10
1.27 0.10
0.80
+0.25 -0.17
6.76 - 0.16
+ 0.35
12

▲Up To Search▲

Price & Availability of HM6287HM6287HSERIES

	To Download HM6287HM6287HSERIES Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .